Taiwanese foundry TSMC is to set up its first design centre in Europe and is looking at a significant leap in memory technology for automotive applications.
The EU Design Centre (EUDC) will be based in Munich is expected to focus on automotive, but will also support chip designs for industrial applications, artificial intelligence (AI), telecoms and the Internet of things (IoT).
With this in mind, TSMC has qualified its 28nm resistive RRAM memory for automotive applications, with a 12nm version expected to meet the same stringent automotive quality requirements with a 6nm version planned. It also planning a 5nm MRAM magnetic memory. Along with MRAM, RRAM is a key replacement for flash memory on process technologies below 16nm. TSMC has 22nm MRAM is in production, and 16nm MRAM is ready for customers with 12nm MRAM is in development.
However TSMC is also validating MRAM and RRAM for future scalability down to 5nm and 6nm respectively. This is a significant step for scaling memory for ADAS and AI chips in vehicles.
The EUDC joins TSMC’s existing global network of nine design centres across Taiwan, the United States, Canada, mainland China and Japan and is expected to open in the third quarter of 2025.
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Automotive was a strong focus for TSMC at its Technology Symposium in Amsterdam today, and TSMC is expecting its 3nm process to be qualified for automotive use later this year. This will be for next generation central AI and ADAS chips, alongside 12nm resistive RRAM memories.
Smart vehicle technology includes automotive-grade advanced packaging, lateral overflow integration capacitor (LOFIC) image sensors for high dynamic range to handle sudden changes in light conditions, enabled by TSMC’s 3D high density metal-insulator-metal (MiM) capacitor
For automotive ADAS, it provides a more than 100 dB LED flicker-free dynamic range without compromising light performance and generation.
For the Internet of things, TSMC has started exploratory development of its 4nm N4e process, aiming to reduce the voltage further from the current value of 0.4V, which will be approaching the threshold voltage. It is also looking at ultra-low leakage SRAM and logic further reduce leakage power to extend battery life.
N3 is expected to be a high-volume and long-running node, with more than 70 new tapeouts as of April 2025. N3E is in high-volume production of flagship mobile and HPC/AI products. N3P entered volume production in Q4 2024.
N3A targets automotive applications, including driver assistance and self-driving technology. This is currently undergoing final defect improvements and on track for AEC Q100 Grade 1 qualification and will be production-ready later in 2025.
Automotive will be responsible for 15% of the $1tn market by 2030, says the company, ahead of the Internet of Things at 10%. Datacentre and AI of course is driving growth, expecting to provide 45% of the market, or $450bn by 2030 with the A16 and A14 process technologies, TSMC is starting a fab in Tauchung, Taiwan, Fab 25, later this year for these technologies.
A16 and A14 are expected to use complementary field-effect transistor (CFET) designs that stack the nFET and pFET vertically, CFET achieves nearly twice the density.
In display technologies, TSMC announced the industry’s first FinFET high voltage platform to be used in foldable/slim OLED and AR glasses. Compared to 28HV, 16HV is expected to reduce DDIC power by around 28% and increase logic density by approximately 41%.
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